2、设计一个序列检测器,对1110010进行检测,编写实验程序。
3、对程序进行仿真测试并给出仿真波形。
4、仿真通过后进行引脚锁定,再进行一次全编译,并下载到实验箱上进行验证。
三、状态机源程序:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY STATEMACHINE IS
PORT(DIN,CLK,RST:IN STD_LOGIC;
SOUT:OUT STD_LOGIC);
END STATEMACHINE;
ARCHITECTURE BEHAV OF STATEMACHINE IS
TYPE STATES IS (S0,S1,S2,S3,S4,S5,S6,S7);
SIGNAL ST,NST:STATES:=S0;
BEGIN
COM:PROCESS(ST,DIN) BEGIN
CASE ST IS
WHEN S0=>IF DIN='1' THEN NST<=S1;ELSE NST<=S0;END IF;
WHEN S1=>IF DIN='1' THEN NST<=S2;ELSE NST<=S0;END IF;
WHEN S2=>IF DIN='1' THEN NST<=S3;ELSE NST<=S0;END IF;
WHEN S3=>IF DIN='1' THEN NST<=S3;ELSE NST<=S4;END IF;
WHEN S4=>IF DIN='1' THEN NST<=S1;ELSE NST<=S5;END IF;
WHEN S5=>IF DIN='1' THEN NST<=S6;ELSE NST<=S0;END IF;
WHEN S6=>IF DIN='1' THEN NST<=S2;ELSE NST<=S7;END IF;
WHEN S7=>IF DIN='1' THEN NST<=S1;ELSE NST<=S0;END IF;
WHEN OTHERS=>NST<=S0;
END CASE;
END PROCESS;
REG:PROCESS (CLK,RST)
BEGIN
IF RST='1' THEN ST<=S0;
ELSIF CLK'EVENT AND CLK='1' THEN ST<=NST;END IF;
END PROCESS REG;
SOUT<='1' WHEN ST=S7 ELSE '0';
END BEHAV;
3、对程序进行仿真测试并给出仿真波形。
4、仿真通过后进行引脚锁定,再进行一次全编译,并下载到实验箱上进行验证。
三、状态机源程序:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY STATEMACHINE IS
PORT(DIN,CLK,RST:IN STD_LOGIC;
SOUT:OUT STD_LOGIC);
END STATEMACHINE;
ARCHITECTURE BEHAV OF STATEMACHINE IS
TYPE STATES IS (S0,S1,S2,S3,S4,S5,S6,S7);
SIGNAL ST,NST:STATES:=S0;
BEGIN
COM:PROCESS(ST,DIN) BEGIN
CASE ST IS
WHEN S0=>IF DIN='1' THEN NST<=S1;ELSE NST<=S0;END IF;
WHEN S1=>IF DIN='1' THEN NST<=S2;ELSE NST<=S0;END IF;
WHEN S2=>IF DIN='1' THEN NST<=S3;ELSE NST<=S0;END IF;
WHEN S3=>IF DIN='1' THEN NST<=S3;ELSE NST<=S4;END IF;
WHEN S4=>IF DIN='1' THEN NST<=S1;ELSE NST<=S5;END IF;
WHEN S5=>IF DIN='1' THEN NST<=S6;ELSE NST<=S0;END IF;
WHEN S6=>IF DIN='1' THEN NST<=S2;ELSE NST<=S7;END IF;
WHEN S7=>IF DIN='1' THEN NST<=S1;ELSE NST<=S0;END IF;
WHEN OTHERS=>NST<=S0;
END CASE;
END PROCESS;
REG:PROCESS (CLK,RST)
BEGIN
IF RST='1' THEN ST<=S0;
ELSIF CLK'EVENT AND CLK='1' THEN ST<=NST;END IF;
END PROCESS REG;
SOUT<='1' WHEN ST=S7 ELSE '0';
END BEHAV;