module bit4(f1hz,fin,doutt,coutt);
input f1hz,fin;
output [15:0]doutt;
output coutt;
wire loadt;
wire cnt_ent,rst_cntt;
wire [3:0]outy1,outy2,outy3,outy4;
wire cout1,cout2,cout3;
testct u1(f1hz,cnt_ent,rst_cntt,loadt);
cnt10 u2(fin,rst_cntt,cnt_ent,outy1,cout1);
cnt10 u3(cout1,rst_cntt,cnt_ent,outy2,cout2);
cnt10 u4(cout2,rst_cntt,cnt_ent,outy3,cout3);
cnt10 u5(cout3,rst_cntt,cnt_ent,outy4,coutt);
reg4b u6(loadt,outy1,doutt[3:0]);
reg4b u7(loadt,outy2,doutt[7:4]);
reg4b u8(loadt,outy3,doutt[11:8]);
reg4b u9(loadt,outy4,doutt[15:12]);
endmodule
module testct(clkk,cnt_en,rst_cnt,load);
input clkk;
output cnt_en,rst_cnt,load;
reg rst_cnt;
reg div2clk;
wire cnt_en,load;
always@(posedge clkk)
begin
div2clk=~div2clk;
end
always@(clkk or div2clk)
begin
if((clkk==0)&(div2clk==0))
rst_cnt=1;
else
rst_cnt=0;
end
assign load=~div2clk;
assign cnt_en=div2clk;
endmodule
module cnt10(clk,rst,ena,outy,cout);
input clk,rst,ena;
output [3:0] outy;
output cout;
reg cout;
reg [3:0]outy;
always@(posedge clk or posedge rst)
begin
if(rst)
outy=0;
else
begin
if(ena)
begin
if(outy<4'b1001)
begin
outy=outy+1;
cout=0;
end
else
begin
outy=0;
cout=1'b1;
end
end
end
end
endmodule
module reg4b(load,din,dout);
input [3:0]din;
input load;
output [3:0]dout;
reg [3:0]dout;
always@(posedge load)
begin
dout=din;
end
endmodule
input f1hz,fin;
output [15:0]doutt;
output coutt;
wire loadt;
wire cnt_ent,rst_cntt;
wire [3:0]outy1,outy2,outy3,outy4;
wire cout1,cout2,cout3;
testct u1(f1hz,cnt_ent,rst_cntt,loadt);
cnt10 u2(fin,rst_cntt,cnt_ent,outy1,cout1);
cnt10 u3(cout1,rst_cntt,cnt_ent,outy2,cout2);
cnt10 u4(cout2,rst_cntt,cnt_ent,outy3,cout3);
cnt10 u5(cout3,rst_cntt,cnt_ent,outy4,coutt);
reg4b u6(loadt,outy1,doutt[3:0]);
reg4b u7(loadt,outy2,doutt[7:4]);
reg4b u8(loadt,outy3,doutt[11:8]);
reg4b u9(loadt,outy4,doutt[15:12]);
endmodule
module testct(clkk,cnt_en,rst_cnt,load);
input clkk;
output cnt_en,rst_cnt,load;
reg rst_cnt;
reg div2clk;
wire cnt_en,load;
always@(posedge clkk)
begin
div2clk=~div2clk;
end
always@(clkk or div2clk)
begin
if((clkk==0)&(div2clk==0))
rst_cnt=1;
else
rst_cnt=0;
end
assign load=~div2clk;
assign cnt_en=div2clk;
endmodule
module cnt10(clk,rst,ena,outy,cout);
input clk,rst,ena;
output [3:0] outy;
output cout;
reg cout;
reg [3:0]outy;
always@(posedge clk or posedge rst)
begin
if(rst)
outy=0;
else
begin
if(ena)
begin
if(outy<4'b1001)
begin
outy=outy+1;
cout=0;
end
else
begin
outy=0;
cout=1'b1;
end
end
end
end
endmodule
module reg4b(load,din,dout);
input [3:0]din;
input load;
output [3:0]dout;
reg [3:0]dout;
always@(posedge load)
begin
dout=din;
end
endmodule