module ABCD(A,B,C,D,F);
input A,B,C,D; output F;
assign F=~(A&B)|(B&D&C);
endmodule

module DFF(din,clk,dout);
input din,clk; output dout;
reg i,o;
always@(posedge clk)
i=din;
wire A=~(i);
always@（posedge clk)
o=A;
assign dout=i&o;
andmodule