LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Reg_374_D IS
PORT(
data:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clk,oe:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END Reg_374_D;
ARCHITECTURE Arch_Reg374D OF Reg_374_D IS
COMPONENT D_ff
PORT(
clk,data:IN STD_LOGIC;
q:OUT STD_LOGIC
);
END COMPONENT;
SIGNAL t:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(clk,oe)
BEGIN
IF(oe='1') THEN
t<="ZZZZZZZZ";
ELSIF(clk'EVENT AND clk='1') THEN
t<=data;
END IF;
END PROCESS;
u0:D_ff PORT MAP(clk,t(0),q(0));
u1:D_ff PORT MAP(clk,t(1),q(1));
u2:D_ff PORT MAP(clk,t(2),q(2));
u3:D_ff PORT MAP(clk,t(3),q(3));
u4:D_ff PORT MAP(clk,t(4),q(4));
u5:D_ff PORT MAP(clk,t(5),q(5));
u6:D_ff PORT MAP(clk,t(6),q(6));
u7:D_ff PORT MAP(clk,t(7),q(7));
END Arch_Reg374D;
麻烦问一下各位为什么这样写并不能实现功能。