module counter_9999(
inputclk,
inputreset_1,
outputreg[3:0]counter
);
always@(negedge reset_1 or posedge clk)begin
if(!reset_1)begin
counter<=4'b0;
end
else begin
if(counter==4'd9)begin
counter<=4'b0;
end
else begin
counter<=counter+4'b1;
end
end
end
endmodule

module dyn_seg(
inputclk,
inputreset_1,
input[4:0]data,
outputreg[7:0]seg
);
wire[3:0]hex;
assign hex=data%10;
always@(negedge reset_1 or posedge clk)begin
if(!reset_1)begin
seg<=8'b0;
end
else begin
case(hex)
4'h0:seg <=8'b11000000;
4'h1:seg<=8'b11111001;
4'h2:seg <=8'b10100100;
4'h3:seg <=8'b10110000;
4'h4:seg <=8'b10011001;
4'h5:seg <=8'b10010010;
4'h6:seg <=8'b10000010;
4'h7:seg <=8'b11111000;
4'h8:seg <=8'b10000000;
4'h9:seg <=8'b10010000;
4'hA:seg <=8'b01110111;
4'hB:seg <=8'b01111100;
4'hC:seg <=8'b00111001;
4'hD:seg <=8'b01011110;
4'hE:seg <=8'b01111001;
4'hF:seg <=8'b01110001;
default:;
endcase
end
end
endmodule

module counter_seg(
inputclk,
inputreset_1,
output[6:0]HEX0,
output[6:0]HEX1,
output[6:0]HEX2,
output[6:0]HEX3,
output[25:0]LED
);
wireclk_200hz;
wireclk_10hz;
wire[3:0]counter;
wire[7:0]seg;
assign LED[25:0]=26'h3ffffff;
counter_9999u_counter_9999(
.clk(clk_10hz),
.reset_1(reset_1),
.counter(counter)
);
clk_genu_clk_gen(
.clk(clk),
.reset_1(reset_1),
.clk_200hz(clk_200hz),
.clk_10hz(clk_10hz)
);
dyn_segu_dyn_seg(
.clk(clk_200hz),
.reset_1(reset_1),
.data(counter),
.seg(seg)
);
assign HEX0[0]=seg[0];
assign HEX0[1]=seg[1];
assign HEX0[2]=seg[2];
assign HEX0[3]=seg[3];
assign HEX0[4]=seg[4];
assign HEX0[5]=seg[5];
assign HEX0[6]=seg[6];
assign HEX1[0]=seg[0];
assign HEX1[1]=seg[1];
assign HEX1[2]=seg[2];
assign HEX1[3]=seg[3];
assign HEX1[4]=seg[4];
assign HEX1[5]=seg[5];
assign HEX1[6]=seg[6];
assign HEX2[0]=seg[0];
assign HEX2[1]=seg[1];
assign HEX2[2]=seg[2];
assign HEX2[3]=seg[3];
assign HEX2[4]=seg[4];
assign HEX2[5]=seg[5];
assign HEX2[6]=seg[6];
assign HEX3[0]=seg[0];
assign HEX3[1]=seg[1];
assign HEX3[2]=seg[2];
assign HEX3[3]=seg[3];
assign HEX3[4]=seg[4];
assign HEX3[5]=seg[5];
assign HEX3[6]=seg[6];
endmodule