timescalelns/100ps
module clk_gen(
inputclk,
inputreset_1,
outputregclk_200hz,
outputregclk_10hz
);
reg[17:0]clk_200hz_cnt;
reg[3:0]clk_10hz_cnt;
parameterclk_200hz_cnt_MAX=17'd124999;
always@(negedge reset_1 or posedge clk)begin
if(!reset_1)begin
clk_200hz_cnt<=17'b0;
clk_200hz<=1'b0;
end
else begin
if(clk_200hz_cnt==clk_200hz_cnt_MAX)begin
clk_200hz_cnt<=17'b0;
clk_200hz<=~clk_200hz;
end
else begin
clk_200hz_cnt<=clk_200hz_cnt+17'b1;
end
end
end
always@(negedge reset_1 or posedge clk_200hz)begin
if(!reset_1)begin
clk_10hz_cnt<=4'b0;
clk_10hz<=1'b0;
end
else begin
if(clk_10hz_cnt==4'd9)begin
clk_10hz_cnt<=4'b0;
clk_10hz<=~clk_10hz;
end
else begin
clk_10hz_cnt<=clk_10hz_cnt+4'b1;
end
end
end
endmodule