数字秒表
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alarm is
port(clk,I:in std_logic;
q:out std_logic);
end alarm;
architecture speaker of alarm is
signal n:integer range 0 to 9;
signal q0:std_logic;
begin
process(clk,I)
begin
if clk'event and clk='1' then
if i<='0' then q0<='0';n<=0;
elsif (i='1' and n<=9 )then
q0<='1';n<=n+1;
else q0<='0';
end if;
end if;
end process;
q<=q0;
end speaker;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count6 is
port(clk,clr,start:in std_logic;
cout:out std_logic;
daout:buffer std_logic_vector(3 downto 0));
end count6;
architecture behave of count6 is
begin
process(clk,clr,start)
begin
if(clr='1') then
daout<="0000";
elsif rising_edge(clk) then
if(start='1')then
if daout="0101" then
daout<="0000";cout<='1';
else
daout<=daout+'1';cout<='0';
end if;
end if;
end if;
end process;
end behave;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count10 is
port(clk: in std_logic;
clr,start: in std_logic;
cout:out std_logic;
daout:buffer std_logic_vector(3 downto 0));
end count10;
architecture behave of count10 is
begin
process(clk,clr,start)
begin
if(clr='1') then
daout<="0000";
elsif rising_edge(clk) then
if(start='1') then
if daout="1001" then
daout<="0000";cout<='1';
else
daout<=daout+'1';cout<='0';
end if;
end if;
end if;
end process;
end behave;
library ieee;
use ieee.std_logic_1164.all;
entity deled is
port(num:in bit_vector(3 downto 0);
led:out bit_vector(6 downto 0));
end;
architecture one of deled is
begin
process(num)
begin
case num(3 downto 0) is
when "0000"=>led<="0111111";
when "0001"=>led<="0000110";
when "0010"=>led<="1011011";
when "0011"=>led<="1001111";
when "0100"=>led<="1100110";
when "0101"=>led<="1101101";
when "0110"=>led<="1111101";
when "0111"=>led<="0000111";
when "1000"=>led<="1111111";
when "1001"=>led<="1101111";
when "1010"=>led<="1110111";
when "1011"=>led<="1111100";
when "1100"=>led<="0111001";
when "1101"=>led<="1011110";
when "1110"=>led<="1111001";
when "1111"=>led<="1110001";
when others=>NULL;
END CASE;
END PROCESS;
END ONE;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity divclk is
port(clk: in std_logic;
clk0:out std_logic);
end divclk;
architecture behave of divclk is
signal count:integer range 0 to 100000;
signal q0: std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
if count=100000 then
count<=0;
q0<=not q0;
else
count<=count+1;
end if;
end if;
end process;
clk0<=q0;
end behave;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity divclk1000 is
port(clk: in std_logic;
clk1:out std_logic);
end divclk1000;
architecture behave of divclk1000 is
signal count:integer range 0 to 1000;
signal q0: std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
if count=1000 then
count<=0;
q0<=not q0;
else
count<=count+1;
end if;
end if;
end process;
clk1<=q0;
end behave;
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY seltime IS
PORT(
clk, clr: INSTD_LOGIC;
DAIN1,DAIN2,DAIN3,DAIN4,DAIN5,DAIN6: INSTD_LOGIC_VECTOR(3 downto 0);
sel : out std_logic_vector ( 2 downto 0);
DAOUT:out STD_LOGIC_VECTOR(3 downto 0));
END seltime;
ARCHITECTURE fun OF seltime IS
SIGNAL count: STD_LOGIC_vector ( 2 downto 0);
BEGIN
sel <= count;
process ( clk)
begin
if (clk 'event and clk='1') then
if ( count >= "101") then
count <= "000";
else
count <= count + 1;
end if;
end if;
end process;
process(count,DAIN1,DAIN2,DAIN3,DAIN4,DAIN5,DAIN6)
begin
if clr='1' then
daout<="0000";
else
case count is
when "000" => daout <= DAIN1(3 downto 0);
when "001" => daout <= DAIN2(3 downto 0);
when "010" => daout <= DAIN3(3 downto 0);
when "011" => daout <= DAIN4(3 downto 0);
when "100" => daout <= DAIN5(3 downto 0);
when "101" => daout <= DAIN6(3 downto 0);
when others => daout <= null;
end case;
end if;
end process;
end fun;

移位寄存器
library ieee;
use ieee.std_logic_1164.all;
entity rlshift is
port(clr,load,clk,s,dir,dil:in bit;
d:in bit_vector(7 downto 0);
q:buffer bit_vector(7 downto 0));
end rlshift;
architecture one of rlshift is
signal q_temp:bit_vector(7 downto 0);
begin
process(clr,load,clk,s,dir,dil)
begin
if clr='0' then q_temp<="00000000";
elsif clk'event and clk='1' then
if (load='1') then
q_temp<=d;
elsif (s='1') then
for i in 7 downto 1 loop
q_temp(i-1)<=q(i);
end loop;
q_temp(7)<=dir;
else
for i in 0 to 6 loop
q_temp(i+1)<=q(i);
end loop;
q_temp(0)<=dil;
end if;
end if;
q<=q_temp;
end process;
end one;

数据比较器
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity comp4 is
port(a,b:instd_logic_vector(3 downto 0);
rst:in std_logic;
AEQB,AGTB,ALTB: out std_logic);
END;
Architecture a of comp4 is
Begin
process(a,b)
Begin
if a>b then AEQB<='0';AGTB<='1';ALTB<='0';
elsif a<b then AEQB<='0';AGTB<='0';ALTB<='1';
elsif a=b then AEQB<='1';AGTB<='0';ALTB<='0';
end if;
END process;
END;

带使能输入及同步清0的增1/减1的3位计数器
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity up_down is
Port(clk,rst,en,up: in std_logic;
Sum: out std_logic_vector(2 downto 0);
Cout: out std_logic);
End;
Architecture a of up_down is
Signal count: std_logic_vector(2 downto 0);
Begin
Process(clk,rst)
Begin
If rst='0' then
Count<=(others=>'0');
Elsif rising_edge(clk) then
If en='1' then
Case up is
When '1' => count<=count+1;
When others =>count<=count-1;
End case;
End if;
End if;
End process;
Sum<=count;
Cout <='1' when en='1' and ((up='1' and count=7) or (up='0' and count=0)) else '0';
End;

多路数据选择器
LIBRARY IEEE;
USE IEEE.Std_logic_1164.ALL;
ENTITY mux_16_1 IS
PORT(en: IN Std_logic;
sel: IN Std_logic_vector(3 DOWNTO 0);
in_signal: IN Std_logic_vector(15 DOWNTO 0);
y: OUT Std_logic);
END mux_16_1;
ARCHITECTURE behavl_case OF mux_16_1 IS
BEGIN
PROCESS(en, sel,in_signal)
BEGIN
IF en='1' THEN
CASE sel IS
WHEN "0000" => y <= in_signal(0);
WHEN "0001" => y <= in_signal(1);
WHEN "0010" => y <= in_signal(2);
WHEN "0011" => y <= in_signal(3);
WHEN "0100" => y <= in_signal(4);
WHEN "0101" => y <= in_signal(5);
WHEN "0110" => y <= in_signal(6);
WHEN "0111" => y <= in_signal(7);
WHEN "1000" => y <= in_signal(8);
WHEN "1001" => y <= in_signal(9);
WHEN "1010" => y <= in_signal(10);
WHEN "1011" => y <= in_signal(11);
WHEN "1100" => y <= in_signal(12);
WHEN "1101" => y <= in_signal(13);
WHEN "1110" => y <= in_signal(14);
WHEN "1111" => y <= in_signal(15);
WHEN OTHERS => y <= 'Z';
END CASE;
ELSE
y <= 'Z';
END IF;
END PROCESS;
END behavl_case;

带clk的数据比较器
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity comp4 is
port(a,b:instd_logic_vector(3 downto 0);
sel_f:instd_logic_vector(1 downto 0);
clk,rst:in std_logic;
AEQB,AGTB,ALTB: out std_logic);
END;
Architecture a of comp4 is
Begin
process(a,b,clk,rst)
Begin
if clk'event and clk='1'then
if rst='0' then
if a>b then AEQB<='0';AGTB<='1';ALTB<='0';
elsif a<b then AEQB<='0';AGTB<='0';ALTB<='1';
elsif a=b then AEQB<='1';AGTB<='0';ALTB<='0';
end if;
end if;
end if;
END process;
END;

3-1计数器
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity counter1 is
port(clk,clr,en: in std_logic;
Q: out std_logic_vector(3 downto 0));
End;
Architecture a of counter1 is
Signal qi : std_logic_vector(3 downto 0);
Begin
process(clk,clr)
Begin
if clk'event and clk='1'then
if clr='1'then qi<=(others=>'0');
else if en='1' then
if qi<"1011" then qi<=qi+1;
else qi<="0000"; End if;
else qi<="0000";
End if;
end if;
end if;
End process;
Q<=qi;
End;

8位计数显示译码电路
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity cnt4e is
port(clk,ena:in std_logic;
Q: BUFFER INTEGER RANGE 0 TO 15;
count:out std_logic);
END cnt4e;
Architecture one of cnt4e is
Begin
process(clk,ena)
Begin
if clk'event and clk='1'then
if ena='1' then
if Q=15 then Q<=0;
count<='0';
elsif Q=14 then Q<=Q+1;
count<='1';
else Q<=Q+1;
end if;
end if;
end if;
End process;
end one;
Library ieee;
Use ieee.std_logic_1164.all;
Entity vhdl2 is
port(a:in std_logic_vector(3 downto 0);
led7s: out std_logic_vector(7 downto 0));
END;
Architecture a of vhdl2 is
Begin
process(A)
Begin
case A(3 DOWNTO 0) is
when"0000"=>led7s<="00111111";
when"0001"=>led7s<="00000110";
when"0010"=>led7s<="01011011";
when"0011"=>led7s<="01001111";
when"0100"=>led7s<="01100110";
when"0101"=>led7s<="01101101";
when"0110"=>led7s<="01111101";
when"0111"=>led7s<="00000111";
when"1000"=>led7s<="01111111";
when"1001"=>led7s<="01101111";
when"1010"=>led7s<="01110111";
when"1011"=>led7s<="01111100";
when"1100"=>led7s<="00111001";
when"1101"=>led7s<="01011110";
when"1110"=>led7s<="01111001";
when"1111"=>led7s<="01110001";
when others=>NULL;
end case;
end process;
end;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count10 is
port(clk: in std_logic;
clr,ena: in std_logic;
cout:out std_logic;
daout:buffer std_logic_vector(3 downto 0));
end count10;
architecture behave of count10 is
begin
process(clk,clr,ena)
begin
if(clr='1') then
daout<="0000";
elsif rising_edge(clk) then
if(ena='1') then
if daout="1001" then
daout<="0000";cout<='1';
else
daout<=daout+'1';cout<='0';
end if;
end if;
end if;
end process;
end behave;
library ieee;
use ieee.std_logic_1164.all;
entity deled is
port(num:in bit_vector(3 downto 0);
led:out bit_vector(7 downto 0));
end;
architecture one of deled is
begin
process(num)
begin
case num(3 downto 0) is
when "0000"=>led<="00111111";
when "0001"=>led<="00000110";
when "0010"=>led<="01011011";
when "0011"=>led<="01001111";
when "0100"=>led<="01100110";
when "0101"=>led<="01101101";
when "0110"=>led<="01111101";
when "0111"=>led<="00000111";
when "1000"=>led<="01111111";
when "1001"=>led<="01101111";
when "1010"=>led<="01110111";
when "1011"=>led<="01111100";
when "1100"=>led<="00111001";
when "1101"=>led<="01011110";
when "1110"=>led<="01111001";
when "1111"=>led<="01110001";
when others=>NULL;
END CASE;
END PROCESS;
END ONE;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity divclk is
port(clk: in std_logic;
clk0:out std_logic);
end divclk;
architecture behave of divclk is
signal count:integer range 0 to 10000000;
signal q0: std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
if count=10000000 then
count<=0;
q0<=not q0;
else
count<=count+1;
end if;
end if;
end process;
clk0<=q0;
end behave;
library ieee;
use ieee.std_logic_1164.all;
entity reg32b is
port(load:in std_logic;
rst:in std_logic;
din:in std_logic_vector(31 downto 0);
dout:out std_logic_vector(31 downto 0));
end reg32b;
architecture behave of reg32b is
signal data:std_logic_vector(31 downto 0);
begin
process(rst,load)
begin
if rst='1' then
data<=(others=>'0');
elsif(load'event and load='1')then
data<=din;
end if;
dout<=data;
end process;
end behave;
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY seltime IS
PORT(
clk: INSTD_LOGIC;
din: INSTD_LOGIC_VECTOR(31 downto 0);
sel : out std_logic_vector ( 2 downto 0);
daout:out STD_LOGIC_VECTOR(3 downto 0));
END seltime;
ARCHITECTURE fun OF seltime IS
SIGNAL count: STD_LOGIC_vector ( 2 downto 0);
BEGIN
sel <= count;
process ( clk)
begin
if (clk 'event and clk='1') then
if ( count >= "111") then
count <= "000";
else
count <= count + 1;
end if;
end if;
end process;
process(count,din(31 downto 0))
begin
case count is
when "000" => daout <= din(3 downto 0);
when "001" => daout <= din(7 downto 4);
when "010" => daout <= din(11 downto 8);
when "011" => daout <= din(15 downto 12);
when "100" => daout <= din(19 downto 16);
when "101" => daout <= din(23 downto 20);
when "110" => daout <= din(27 downto 24);
when "111" => daout <= din(31 downto 28);
when others => daout <= null;
end case;
end process;
end fun;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity testctl is
port(clk: in std_logic;
tsten:out std_logic;
clr_cnt:out std_logic;
load:out std_logic);
end testctl;
architecture behave of testctl is
signal div2clk:std_logic;
begin
process(clk)
begin
if(clk'event and clk='1')then
div2clk<=not div2clk;
end if;
end process;
process(clk,div2clk)
begin
if(clk='0' and div2clk='0')then
clr_cnt<='1';
else
clr_cnt<='0';
end if;
end process;
load<=not div2clk;
tsten<=div2clk;
end behave;

哇偶

楼主还在吗，求解释
Begin
If CR='0' then
T<="0000";
Elsif rising_edge(clk) then
If LD='1' then
Case (ET and EP) is
When '1' => T<=T+1;
When others =>T<=T;
End case;
Else T<=D;
End if;
End if;