顶层模块：
modulemy_uart{
clk,rst_n,rsx_rx,
rsx_tx
};
input clk;//50M时钟
input rst_n;//复位信号低电平有效
input rsx_rx;//
output rsx_tx;
wire bps_start1,bps_start2; //声明发送、接收波特率启动信号
wire clk_bps1,clk_bps2; //声明中间采样位置
wire[7:0] rx_data;//数据信号
wire rx_int;//高电平有效，接收状态
//-----------------------------------------------------------------------
my_speed speed_rx( //例化接收波特率
.clk(clk),
.rst_n(rst_n),
.bps_start(bps_start1),
.clk_bps(clk_bps1)
);
my_rx uart_rx( //例化数据接收模块
.clk(clk),
.rst_n(rst_n),
.rsx_rx(rsx_rx),
.clk_bps(clk_bps1),
.bps_start(bps_start1),
.rx_data(rx_data),
.rx_int(rx_int)
);
//-----------------------------------
my_speed speed_tx( //例化发送波特率
.clk(clk),
.rst_n(rst_n),
.bps_start(bps_start2),
.clk_bps(clk_bps2)
);
my_tx uart_tx( //例化数据发送模块
.clk(clk),
.rst_n(rst_n),
.rsx_tx(rsx_tx),
.clk_bps(clk_bps2),
.bps_start(bps_start2),
.rx_data(rx_data),
.rx_int(rx_int)
);

波特率选择模块
module my_speed{
};
input clk;
input rst_n;
input bps_start; //由my_rx提供；
outputclk_bps; //产生中间采样位置，一个时钟周期的高电平
//------------------------------------------------------------------------
//50m时钟，计数波特率
parameterbps9600 = 5207,
bps115200 = 433;
parameterbps9600_2 = 2603,
bps115200_2 = 216;
//------------------------------------------------------------------------------
reg[12:0] bps_para;
reg[12:0] bps_para_2;
reg[12:0] cnt;
reg bps_start_r;
//------------------------------------------------------------------
reg bps_ctrl; //波特率选择器
//----------------------------------------------------------------
always @(posedge clk or negedge rst_n) begin
if(!rst_n) bps_ctrl <= 1'b0;
else begin
case(bps_ctrl)
1'b0: begin
bps_para <= bps9600;
bps_para_2 <= bps9600_2;
end
1'b1: begin
bps_para <= bps115200;
bps_para_2 <= bps115200_2;
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) cnt <= 13'd0;
else if(cnt == bps_para || !bps_start) cnt <= 13'd0;
else cnt <= cnt + 1'd1;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) clk_bps_r = 1'b0;
else if(cnt == bps_para_2) clk_bps_r <= 1'b1;
else clk_bps_r <= 1'b0;
end
assign clk_bps = clk_bps_r; //产生中间采样位置，并反馈
endmodule