module Verilog1(clk50M,reset,z);
input clk50M;
input reset;
output reg [9:0] z;
reg[4:0] state;
reg[23:0]count;wire clk4hz;
parameter s0='d0,s1='d1,s2='d2,s3='d3,s4='d4,s5='d5,s6='d6,s7='d7,s8='d8,s9='d9;
always @(posedge clk50M)
begin if(count==12500000) count<=0;
else count<=count+1;
end
assign clk4hz=count[23];
always @(posedge clk4hz)
begin if(reset) state<=s0;
else case(state)
s0: state<=s1; s1: state<=s2;
s2: state<=s3; s3: state<=s4;
s4: state<=s5; s5: state<=s6;
s6: state<=s7; s7: state<=s8;
s8: state<=s9; s9: state<=s0;
default: state<=s0;
endcase
end
always @(state)
begin case(state)
s0:z<=10'b0000000000;
s1:z<=10'b1000000001;
s2:z<=10'b1100000011;
s3:z<=10'b1110000111;
s4:z<=10'b1111001111;
s5:z<=10'b0000110000;
s6:z<=10'b0001111000;
s7:z<=10'b0011111100;
s8:z<=10'b0111111110;
s9:z<=10'b1111111111;
default:z<=10'b1000000001;
endcase;
end
endmodule