从capture导出网表到allegro时，原理图中只有一个电阻，没有连线，单纯为了测试。电阻的pcb footprint已经填好，allegro路径也设置好了，但是导出网表的时候出现could not open.......pstxprt.dat。具体的错误如下：
#77 ERROR(SPCODD-77): Could not open file D:\PROJECTS\PADS\ALLEGRO_TEST\allegro/pstxprt.dat.
You might be trying to reuse a design with an inaccessible state file. To reuse a design, ensure that the design being reused is treated as a subdesign and the subdesign state file is accessible and readable. To create the subdesign state file, use the GEN_SUBDESIGN directive.
ERROR(SPCODD-382): Error at line 1 in file D:\PROJECTS\PADS\ALLEGRO_TEST\allegro/pstxprt.dat. Error loading the parts list file
#1 ERROR(ORCAP-36026): Unable to read logical netlist data.
使用的软件版本为16.6
求贴吧的各位大神看一下，这个应该怎么解决啊，谢谢大家！！
#77 ERROR(SPCODD-77): Could not open file D:\PROJECTS\PADS\ALLEGRO_TEST\allegro/pstxprt.dat.
You might be trying to reuse a design with an inaccessible state file. To reuse a design, ensure that the design being reused is treated as a subdesign and the subdesign state file is accessible and readable. To create the subdesign state file, use the GEN_SUBDESIGN directive.
ERROR(SPCODD-382): Error at line 1 in file D:\PROJECTS\PADS\ALLEGRO_TEST\allegro/pstxprt.dat. Error loading the parts list file
#1 ERROR(ORCAP-36026): Unable to read logical netlist data.
使用的软件版本为16.6
求贴吧的各位大神看一下，这个应该怎么解决啊，谢谢大家！！
