转一篇GF的报道，18年中期7nm第一个版本就有了，别买了，等19年上razen3,lol
Earlier in the week, I wrote about my meeting with Gary Patton the day before GLOBALFOUNDRIES presented their 7nm process as IEDM. See Gary Patton on GF, IBM, 7nm, EUV, and More for more details. Earlier in the morning, Intel had announced details of their 10nm process (roughly equivalent, despite the different number). See Intel 10nm for details.
The following morning, Basanth Jagannathan stood up gave details of the GF process. The one-paragraph summary is that it has 2.8X the routed density over 14nm, with 40% more performance or 55% less power. It is all optical, but designed for later EUV insertion with no changes required to the designs.
7nm Details
The table above shows the key pitches. The fin is 30nm SAQP, the gate is 56nm SADP. Metal0 is 40nm SADP. One big decision they took was that, as a foundry, they needed lots of flexibility. A tighter metal pitch would require SAQP and also be unidirectional and with a fixed width (this is the opposite decision to the one Intel made, given their different businesses). By using SADP, they get to have just a preferred direction, what they call NDR (non-default route), and also the capability to vary the width of the lines (and vias). This also gives superior EM performance.
They have two sizes of standard cells, dense cells with 240nm height and 2 fins, HPC cells with 360nm height and 4 fins (pictured above). The flop is 0.36X the size in 14nm, an aoi21 gate is 0.37X the size. This gives a 2.8X improvement in routed logic density. This is not just the process shrink itself, but a mixture of the process, along with library design, pin configuration, router optimization, and design rule synergy. Using design-technology co-optimization (DTCO) numbers seems to be the new normal, since a straightforward shrink alone doesn't keep on the Moore's Law trajectory.
The overall performance and power is shown in the graph above. There is a performance increase of over 40%, or a power decrease of over 55% (and obviously intermediate tradeoff points). The green line in the graph shows the additional performance using the HPC 4-fin logic cells (for ultimate single thread performance, at the cost of increased power).
Another key decision (and another one that differs from the tradeoff that Intel made) is to take advantage of the SADP (as opposed to SAQP) to allow wide metal and vias when needed. In the case of a high-speed SerDes buffer, this gave an increase in rise time of about 30%.
The fin profile (which is SAQP at 30nm pitch) is carefully controlled, leading to an improvement in drain-induced barrier lowering (DIBL) versus Leff compared to the GF/Samsung 14nm process. The above diagram shows both a photo of the fin cross-section and the comparison. the fins are undoped. There is a cobalt trench metal contact. Basanth pointed out that when layouts are small, vertical resistance is important and Co is 40% better.
Moving on from the basic device architecture to SRAM, the process has a bit cell of 0.0269um2, and a higher performance cell with an area of 0.0353um2. This delivers a 2.3X increase in density, and a 2X increase in speed, due to reduced bitline capacitance and improved read current.
BEOL
The above diagram shows the metal stack, which is a copper/lowK BEOL. There are multiple stacks offered, with two different versions shown in the table on the left. 1X layers are SADP unidirectional. 2X layers are single patterned with a preferred orientation. 3.2X layers are bidirectional. The 18X layers also have an MIMcap integrated for decoupling, with much better performance than the prior 14nm process.
The BEOL density scaling is not limited my electro-migration. 7nm has a 100X improvement over 14nm due to liner changes, capacitance material changes, and material changes. This has a big impact on the power grid. Without the material changres, the power grid with be 3X larger, but instead is 4X smaller.
EUV
The 7nm process has been designed to go into volume manufacturing using 193i lithography, with the option of EUV insertion later for MEOL contacts, BEOL vias (on lower levels) and cut masks. It requires no design updates and so means EUV can be introduced rapidly once the performance in manufacturing is proven. The number of critical masks is reduced by 25% with EUV, due to the reduced need for multiple patterning on the affected layers. The micrograph above shows EUV use
Earlier in the week, I wrote about my meeting with Gary Patton the day before GLOBALFOUNDRIES presented their 7nm process as IEDM. See Gary Patton on GF, IBM, 7nm, EUV, and More for more details. Earlier in the morning, Intel had announced details of their 10nm process (roughly equivalent, despite the different number). See Intel 10nm for details.
The following morning, Basanth Jagannathan stood up gave details of the GF process. The one-paragraph summary is that it has 2.8X the routed density over 14nm, with 40% more performance or 55% less power. It is all optical, but designed for later EUV insertion with no changes required to the designs.
7nm Details
The table above shows the key pitches. The fin is 30nm SAQP, the gate is 56nm SADP. Metal0 is 40nm SADP. One big decision they took was that, as a foundry, they needed lots of flexibility. A tighter metal pitch would require SAQP and also be unidirectional and with a fixed width (this is the opposite decision to the one Intel made, given their different businesses). By using SADP, they get to have just a preferred direction, what they call NDR (non-default route), and also the capability to vary the width of the lines (and vias). This also gives superior EM performance.
They have two sizes of standard cells, dense cells with 240nm height and 2 fins, HPC cells with 360nm height and 4 fins (pictured above). The flop is 0.36X the size in 14nm, an aoi21 gate is 0.37X the size. This gives a 2.8X improvement in routed logic density. This is not just the process shrink itself, but a mixture of the process, along with library design, pin configuration, router optimization, and design rule synergy. Using design-technology co-optimization (DTCO) numbers seems to be the new normal, since a straightforward shrink alone doesn't keep on the Moore's Law trajectory.
The overall performance and power is shown in the graph above. There is a performance increase of over 40%, or a power decrease of over 55% (and obviously intermediate tradeoff points). The green line in the graph shows the additional performance using the HPC 4-fin logic cells (for ultimate single thread performance, at the cost of increased power).
Another key decision (and another one that differs from the tradeoff that Intel made) is to take advantage of the SADP (as opposed to SAQP) to allow wide metal and vias when needed. In the case of a high-speed SerDes buffer, this gave an increase in rise time of about 30%.
The fin profile (which is SAQP at 30nm pitch) is carefully controlled, leading to an improvement in drain-induced barrier lowering (DIBL) versus Leff compared to the GF/Samsung 14nm process. The above diagram shows both a photo of the fin cross-section and the comparison. the fins are undoped. There is a cobalt trench metal contact. Basanth pointed out that when layouts are small, vertical resistance is important and Co is 40% better.
Moving on from the basic device architecture to SRAM, the process has a bit cell of 0.0269um2, and a higher performance cell with an area of 0.0353um2. This delivers a 2.3X increase in density, and a 2X increase in speed, due to reduced bitline capacitance and improved read current.
BEOL
The above diagram shows the metal stack, which is a copper/lowK BEOL. There are multiple stacks offered, with two different versions shown in the table on the left. 1X layers are SADP unidirectional. 2X layers are single patterned with a preferred orientation. 3.2X layers are bidirectional. The 18X layers also have an MIMcap integrated for decoupling, with much better performance than the prior 14nm process.
The BEOL density scaling is not limited my electro-migration. 7nm has a 100X improvement over 14nm due to liner changes, capacitance material changes, and material changes. This has a big impact on the power grid. Without the material changres, the power grid with be 3X larger, but instead is 4X smaller.
EUV
The 7nm process has been designed to go into volume manufacturing using 193i lithography, with the option of EUV insertion later for MEOL contacts, BEOL vias (on lower levels) and cut masks. It requires no design updates and so means EUV can be introduced rapidly once the performance in manufacturing is proven. The number of critical masks is reduced by 25% with EUV, due to the reduced need for multiple patterning on the affected layers. The micrograph above shows EUV use
