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id的联系方式。。有需要可以联系


IP属地:四川1楼2014-02-17 13:59回复
    你的满意是我的目的


    IP属地:四川3楼2014-02-20 14:10
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      有问题可以留贴,有空给解答。。。


      IP属地:四川6楼2014-02-26 14:03
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        有问题,必解答。。。。


        IP属地:四川8楼2014-03-04 13:50
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          我准备用可编程器件 做几个 有创意的案例 不要传统的数字钟 密码锁 交通灯等 比如 用点阵显示简单动画 这类的…… 麻烦给出出建议


          IP属地:吉林9楼2014-03-04 14:02
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            比如说我写了两个子程序,程序A是八段数码管1,2,3,4,5这样变,程序B是5,4,3,2,1这样变,然后我想根据情况执行,比如我按下一个键A,这时候就执行程序A,按下键B就执行程序B,我该用什么语句写这个?


            10楼2014-03-04 23:19
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              一个按键选择嘛,程序A,B单独同时工作,只是你的按键选择数码管输出程序A还是程序B的值


              IP属地:四川11楼2014-03-06 12:33
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                IP属地:四川12楼2014-03-10 13:08
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                  不知道为什么不在这个帖子里留问题,有问题必解答


                  IP属地:四川13楼2014-03-11 12:07
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                    八位数码管扫描显示程序,要求显示12345678 间隔四秒显示56789ABC 间隔四秒显示3456789A 再隔4秒显示
                    456789AB 我这里有12345678显示的程序如下
                    LIBRARY IEEE;
                    USE IEEE.STD_LOGIC_1164.ALL;
                    USE IEEE.STD_LOGIC_UNSIGNED.ALL;
                    ENTITY chenyongqiang IS
                    PORT ( CLK : IN STD_LOGIC;
                    SG : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --段控制信号输出
                    BT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );--位控制信号输出
                    END;
                    ARCHITECTURE one OF chenyongqiang IS
                    SIGNAL CNT8 : STD_LOGIC_VECTOR(2 DOWNTO 0);
                    SIGNAL A : INTEGER RANGE 0 TO 15;
                    BEGIN
                    P1: PROCESS( CNT8 )
                    BEGIN
                    CASE CNT8 IS
                    WHEN "000" => BT <= "00000001" ; A <= 1 ;
                    WHEN "001" => BT <= "00000010" ; A <= 2 ;
                    WHEN "010" => BT <= "00000100" ; A <= 3 ;
                    WHEN "011" => BT <= "00001000" ; A <= 4 ;
                    WHEN "100" => BT <= "00010000" ; A <= 5 ;
                    WHEN "101" => BT <= "00100000" ; A <= 6 ;
                    WHEN "110" => BT <= "01000000" ; A <= 7 ;
                    WHEN "111" => BT <= "10000000" ; A <= 8 ;
                    WHEN OTHERS => NULL ;
                    END CASE ;
                    END PROCESS P1;
                    P2: PROCESS(CLK)
                    BEGIN
                    IF CLK'EVENT AND CLK = '1' THEN CNT8 <= CNT8 + 1;
                    END IF;
                    END PROCESS P2 ;
                    P3: PROCESS( A ) --译码电路
                    BEGIN
                    CASE A IS
                    WHEN 0 => SG <= "0111111"; WHEN 1 => SG <= "0000110";
                    WHEN 2 => SG <= "1011011"; WHEN 3 => SG <= "1001111";
                    WHEN 4 => SG <= "1100110"; WHEN 5 => SG <= "1101101";
                    WHEN 6 => SG <= "1111101"; WHEN 7 => SG <= "0000111";
                    WHEN 8 => SG <= "1111111"; WHEN 9 => SG <= "1101111";
                    WHEN 10 => SG <= "1110111"; WHEN 11 => SG <= "1111100";
                    WHEN 12 => SG <= "0111001"; WHEN 13 => SG <= "1011110";
                    WHEN 14 => SG <= "1111001"; WHEN 15 => SG <= "1110001";
                    WHEN OTHERS => NULL ;
                    END CASE ;
                    END PROCESS P3;
                    END;


                    IP属地:上海14楼2014-03-12 15:14
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                      有免费解答问题,咋不能问。。。


                      IP属地:四川15楼2014-03-13 12:37
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                        楼主麻烦看一下程序是什么问题,谢谢!
                        ---------------hugong
                        library IEEE;
                        use IEEE.STD_LOGIC_1164.ALL;
                        use IEEE.STD_LOGIC_ARITH.ALL;
                        use IEEE.STD_LOGIC_UNSIGNED.ALL;
                        entity test_yunsuan is
                        Port ( CLK : in STD_LOGIC;
                        disvaluein : in STD_LOGIC_VECTOR (3 downto 0);
                        disvalueout0 : out STD_LOGIC_VECTOR (3 downto 0);
                        disvalueout1 : out STD_LOGIC_VECTOR (3 downto 0));
                        end test_yunsuan;
                        architecture ben of test_yunsuan is
                        signal A:std_logic_vector(7 downto 0):="00000000";
                        signal B0:std_logic_vector(7 downto 0):="00000000";
                        signal B1:std_logic_vector(7 downto 0):="00000000";
                        signal X:std_logic_vector(7 downto 0):="00000000";
                        begin
                        process(CLK)
                        variable flag:std_logic;
                        begin
                        IF CLK' EVENT AND CLK='1' THEN
                        case disvaluein is
                        when "1101" =>B0<=B0&A;
                        flag:='1';
                        when "1110" =>B0<=B0&A;
                        flag:='0';
                        when "1111" =>B1<=B1&A;
                        if flag='1' then
                        X<=(((B0(7)&B0(6)&B0(5)&B0(4))+(B1(7)&B1(6)&B1(5)&B1(4)))*"1010")+(B0(3)&B0(2)&B0(1)&B0(0))+(B1(3)&B1(2)&B1(1)&B1(0));
                        else X<=((B0(7)&B0(6)&B0(5)&B0(4))*"1010")-((B1(7)&B1(6)&B1(5)&B1(4))*"1010")+(B0(3)&B0(2)&B0(1)&B0(0))-(B1(3)&B1(2)&B1(1)&B1(0));
                        end if;
                        when others =>A<=A&disvaluein;
                        X<=X&disvaluein;
                        end case;
                        END IF;
                        end process;
                        end ben;
                        错误信息:Error (10327): VHDL error at test_yunsuan.vhd(33): can't determine definition of operator ""+"" -- found 5 possible definitions
                        程序中的这一句这一句:
                        X<=(((B0(7)&B0(6)&B0(5)&B0(4))+(B1(7)&B1(6)&B1(5)&B1(4)))*"1010")+(B0(3)&B0(2)&B0(1)&B0(0))+(B1(3)&B1(2)&B1(1)&B1(0));


                        16楼2014-03-14 20:32
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                          你这个是库的问题,无法决定你的加法器的运算,并且你的程序这样写得比较有问题,你把这几个库实现什么功能看一下吧,你就知道怎么修改了


                          IP属地:四川17楼2014-03-14 21:09
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                            听说十五个字可以得经验,我来试试,顺便帮卤煮顶一下,卤煮不用谢


                            IP属地:四川19楼2014-03-18 12:14
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                              大神想问下 这个循环哪里出错了 (n位加法器)
                              library IEEE;
                              use IEEE.STD_LOGIC_1164.ALL;
                              use ieee.std_logic_arith.all;
                              use ieee.std_logic_unsigned.all;
                              entity adder is
                              generic(N:integer);
                              Port ( cin: in STD_LOGIC;
                              a,b: in STD_LOGIC_vector(N downto 1);
                              c:out std_logic_vector(N downto 1);
                              cout:out std_logic
                              );
                              end adder;
                              architecture behaviour of adder is
                              signal m:std_logic_vector(N-1 downto 1);
                              begin
                              c(1) <= a(1) xor b(1) xor cin;
                              m(1) <= (a(1) AND b(1)) OR (a(1) AND cin) OR (b(1) AND cin);
                              for i in 2 TO N-1 loop
                              c(i) <= a(i) XOR b(i) XOR m(i-1);
                              m(i) <= (a(i)AND b(i)) OR (m(i-1) AND a(i)) OR (m(i-1) AND b(i));
                              end loop;
                              c(N) <= a(N) XOR b(N) XOR m(N-1);
                              cout <= (a(N) AND b(N)) OR (a(N)AND m(N-1)) OR (b(N) AND m(N-1));
                              end behaviour;


                              21楼2014-03-19 14:56
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