回复：如果你有verilog相关的问题，请进。

请问一下 怎么用spi接口电路实现 主时钟频率100M，输出时钟频率可调

如何用Verilog实现定点补码加法啊，两个数都是原码输入，最后的得数要求补码输出，小弟是软件专业的，头一次接触这种硬件的课设，不是很懂。

你好，首先在这里谢谢你，也希望你能给解答。这段代码，我想实现的是I2C接口电路，实现I2C写协议下的信息传送，每次启动传送16bit的数据。
下面是代码，我编译过，可是错了，我也不知道怎么错的，怎么修改，请指教。
module i2c_master_model (scl, sda);
inout scl;
inout sda;
parameter slave_addr_reg = 7'b0110101; //slave addr
int i;
reg R_scl = 1'bz;
reg R_sda = 1'bz;
reg clk = 0;
always #(1329.1125) clk = !clk;
assign scl = R_scl;
assign sda = R_sda;
task start; //start condition
@(posedge clk);
R_sda = 1;
R_scl = 1;
@(posedge clk);
R_sda = 0;
@(posedge clk);
R_scl = 0;
end task
task stop; //stop condition
R_sda = 0;
@(posedge clk);
R_scl = 1;
@(posedge clk);
R_sda = 1;
@(posedge clk);
R_scl = 1'bz;
@(posedge clk);
@(posedge clk);
R_sda = 1'bz;
end task
task rw_slave_addr(input [6:0] slave_addr, input rw);
for(i=6; i>=0; i--;)
begin
@(posedge clk);
R_sda = slave_addr[i];
@(posedge clk);
R_scl = 1;
@(posedge clk);
@(posedge clk);
R_scl = 0;
end
@(posedge clk);
R_sda = rw;
@(posedge clk);
R_scl = 1;
@(posedge clk);
@(posedge clk);
R_scl = 0;
@(posedge clk);
R_sda = 1'bz;
@(posedge clk);
R_scl = 1;
if(sda != 0) $display("ACK error at time: %t", $time);
@(posedge clk);
@(posedge clk);
R_scl = 0;
@(posedge clk);
end task
task send_byte(input [7:0] send_byte);
for(i=7; i>=0; i--) begin
R_sda = send_byte[i];
@(posedge clk);
R_scl = 1;
@(posedge clk);
@(posedge clk);
R_scl = 0;
@(posedge clk);
end
R_sda = 1'bz;
@(posedge clk);
R_scl = 1'b1;
if(sda != 0) $display("ACK error at time: %t", $time);
@(posedge clk);
@(posedge clk);
R_scl = 0;
@(posedge clk);
end task
task recv_byte(output [7:0] recv_dat);
for(i=7; i>=0; i--) begin
@(posedge clk);
R_scl = 1;
recv_dat[i] = sda;
@(posedge clk);
@(posedge clk);
R_scl = 0;
@(posedge clk);
end task
R_sda = 1'b0; //send ACK
@(posedge clk);
R_scl = 1;
@(posedge clk);
@(posedge clk);
R_scl = 0;
@(posedge clk);
R_sda = 1'bz;
endtask
task recv_byte_noack(output [7:0] recv_dat);
for(i=7; i>=0; i--) begin
@(posedge clk);
R_scl = 1;
recv_dat[i] = sda;
@(posedge clk);
@(posedge clk);
R_scl = 0;
@(posedge clk);
end task
R_sda = 1'b1; //send NOACK
@(posedge clk);
R_scl = 1;
@(posedge clk);
@(posedge clk);
R_scl = 0;
@(posedge clk);
R_sda = 1'bz;
end task
task write_reg(input [7:0]addr, input [7:0] dat);
start;
rw_slave_addr(slave_addr_reg, 0);
send_byte(addr);
send_byte(dat);
stop;
end task
task read_reg(input [7:0] addr, output [7:0] recv_dat);
start;
rw_slave_addr(slave_addr_reg, 0);
send_byte(addr);
start;
rw_slave_addr(slave_addr_reg, 1);
recv_byte_noack(recv_dat);
stop;
end task
task write_reg_2byte(input [7:0]addr, input [15:0] dat);
start;
rw_slave_addr(slave_addr_reg, 0);
send_byte(addr);
send_byte(dat[15:8]);
send_byte(dat[7:0]);
stop;
end task
task read_reg_2byte(input [7:0] addr, output [15:0] recv_dat);
start;
rw_slave_addr(slave_addr_reg, 0);
send_byte(addr);
start;
rw_slave_addr(slave_addr_reg, 1);
recv_byte_noack(recv_dat[15:8]);
recv_byte_noack(recv_dat[7:0]);
stop;
end task

楼主，又打搅你了，还是不想把宏功能那部分放弃。。。。我后来把220model和altera_mf两个库加了进去（不大确定，应该是这两个），木有错误了，但在我add to wave 想看输入和输出的时候，那里没有我的端口，请问怎么回事

楼主，我决定自己写一个12X12的有符号乘法器，不知道感觉不大对，能帮我看看么。。。。因为有负数，所以我就考虑要不要补码，还有输出到底是23位还是24位我也不确定。。。
module 12X12(clock,dataa,datab,result)
input clock;
input signed [11:0] dataa,datab;//输入12位有符号整数
output[22:0] result;//23位的输出，1符号位+22位数字
reg [22:0] result;
reg [11:0] x1,x2,x3,x4;//x1，x2存放输入变量；x3，x4存放变量的原码
reg x5; //存放输出的符号位
reg[21:0] x6; //22位寄存器，存放22位有效数字相乘结果
reg[22:0] x7; //存放输出数据的原码
always@ (posedge clock)
begin
x1<=dataa; //寄存器赋值
x2<=datab;
x3<=(x1[11]==0)?x1:{1'b1,~x1[10:0]+1'b1}; //判断最高位是否为1，即输入是否为负数，是
就取其补码
x4<=(x2[11]==0)?x2:{1'b1,~x2[10:0]+1'b1};//同上
x5<=x3[11]^x4[11]; //两数符号位异或
x6<=x3[10:0]*x4[10:0]; //11位有效数字相乘
x7<={x5,x6}; //输出的原码，由符号位+有效数字组成
result<=(x7[22]==0)?x7:[1'b1,~x7[21:0]+1'b1];//判断输出是否为负数，是就变为补码
end
endmodule

module mult12X12(clock,dataa,datab,result);
output [23:0] result;
input clock;
input signed [11:0] dataa;
input signed [11:0] datab;
reg signed [11:0] dataa_reg;
reg signed [11:0] datab_reg;
reg signed [23:0] result;
wire signed [23:0] mult_result;
assign mult_result =dataa_reg*datab_reg;
always@(posedge clock)
begin
dataa_reg<=dataa;
datab_reg<=datab;
result<=mult_result;
end
endmodule
就是result的波形那里搞不懂怎么会这样

你的datab根本不是一个时钟一个数据啊，但是result会变化是很正常的，因为他是纯组合逻辑的

大神帮忙看一下这个错误被